1. Field of the Invention
This invention relates to a family of asynchronous stored state sequential circuits and more particularly to such circuits that provide for hazard-free and race-free implementations.
2. Description of the Prior Art
Asynchronous binary circuits are circuits that are activated on receipts of input signals without the requirement of a clock to provide timing signals for synchronization of that operation. Such asynchronous circuits can be employed to create larger asynchronous systems and networks which again operate without being driven by a clock or timing signals. Examples of such prior art synchronous circuits are given in the Clark U.S. Pat. Nos. 4,237,447 and 4,251,879, both of which were issued on applications filed on May 2, 1979. Synchronous state machines are employed in a number of different types of digital systems and particularly in digital data processors. Examples of such synchronous state machines are given in the Ferguson et al. U.S. Pat. No. 3,886,523 and also in the Barton et al. U.S. Pat. No. 3,978,452. The Barton et al. patent discloses a network of data processors which accommodate asynchronous data transfer therebetween by way of data buffers in each processor, each processor being synchronous or clock driven. Such machine state control systems or state machines control the phasing of the operational states of the processor or other digital device. As distinct from such prior art state machines, the present invention is directed toward an asynchronous stored state machine as is further described below.
Prior art asynchronous sequential circuits required large quantities of random logic and a resultant high component count. Furthermore, the circuit complexity of conventional asynchronous state machines increases rapidly as the number of states and the inputs to the state machine increases. As a result, the implementation of reliable machines with more than a relatively small number of states and inputs thereto becomes extremely difficult.
The employment of field programmable read only memories (ROM's) simplifies the process of realizing asynchronous sequential circuits by allowing the development of stored state techniques. Such a technique has been applied to asynchronous sequential circuits such as described by J. L. Huertas and J. I. Acha, "Self-synchronization of Asynchronous Sequential Circuits Employing a General Clock Function", IEEE Transactions on Computers, March, 1976, pp. 297-300. In the machines disclosed therein, an internal clock pulse is generated which is required only when the next-state variables and the present-state variables are different. However, such machines do not provide a signalling protocol between like elements of a system which must be provided to delimit data transmissions due to the lack of a system clock.
It is then an object of the present invention to provide an improved asynchronous sequential circuit.
It is another object of the present invention to provide an improved asynchronous circuit which can communicate with similar circuits by delimiting data transmissions without requiring a systems clock.
It is still another object of the present invention to provide an improved asynchronous sequential circuit that is nevertheless hazard-free and race-free.